Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 592

Pulse output part pulse output mask
■Address
Name
Pulse output part pulse output mask 0 (B0) (usr_wreg_142)
Pulse output part pulse output mask 1 (B0) (usr_wreg_143)
Pulse output part pulse output mask 0 (B1) (usr_wreg_144)
Pulse output part pulse output mask 1 (B1) (usr_wreg_145)
Pulse output part pulse output mask 0 (B2) (usr_wreg_146)
Pulse output part pulse output mask 1 (B2) (usr_wreg_147)
Pulse output part pulse output mask 0 (E0) (usr_wreg_148)
Pulse output part pulse output mask 1 (E0) (usr_wreg_149)
Pulse output part pulse output mask 0 (E1) (usr_wreg_14A)
Pulse output part pulse output mask 1 (E1) (usr_wreg_14B)
Pulse output part pulse output mask 0 (E2) (usr_wreg_14C)
Pulse output part pulse output mask 1 (E2) (usr_wreg_14D)
■Description
Enables or disables the pulse output.
Name
Pulse output part pulse output
mask 0
Pulse output part pulse output
mask 1
CH0 to CHF
• 1: Enable
• 0: Disable
(1) IOB0_DIO485_O (for I/O control)
• 1: Enable
• 0: Disable
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
APPX
590
Appendix 4 FPGA register
b15 b14 b13 b12 b11
CHF CHE CHD CHC CHB
0 (fixed)
b10 b9 b8 b7 b6
CHA CH9 CH8 CH7 CH6
FPGA register address
1000_B284H
1000_B286H
1000_B288H
1000_B28AH
1000_B28CH
1000_B28EH
1000_B290H
1000_B292H
1000_B294H
1000_B296H
1000_B298H
1000_B29AH
b5 b4 b3 b2 b1
CH5 CH4 CH3 CH2 CH1
b0
CH0
(1)