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Reset sequence
CLKIN_SYS
(I)
clk100m
(Internal)
H/W reset
(I) L
RSTL
PLL lock signal
(I) L
PLL_LOCK
H/W reset (for PLL)
(O) L
rst_hw_n
System reset
(O) L
rst_n
DDR3L SDRAM
(Internal)
FPGA external
(Internal)
terminal
Internal operation
(Internal)
start/stop
(1) After the H/W reset is released, the reset is executed until the PLL lock becomes enabled. Circuits other than the PLL do not operate.
(2) Switch the connection of the FPGA external terminal inside the FPGA according to the type of circuit board to be connected.
(3) The MCU is notified of the DDR3L SDRAM calibration end. The MCU sets internal operation start/stop to Start(1) and then starts the operation.
PLL lock period
1ms
2-stage FF + SR-FF
(CLKIN_SYS)
5clk
(clk100m)
Resetting
Resetting
Resetting
(1)
(2)
Calibrating
FPGA external terminal connection completed
Stop
(3)
Calibration completed
Start
11 FPGA INTERNAL CIRCUIT
11.4 User Circuit Block
11
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Table of Contents
Troubleshooting
