Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 721

No. Word Target bit of logging data
offset (uc_logdat_clk100m_reg)
160 11 160
161 161
162 162
163 163
164 164
165 165
166 166
167 167
168 168
169 169
170 170
171 171
172 172
173 173
174 174
175 175
Logging target list
User circuit logging mode is the non-
time division mode
32-bit ring counter (2-phase multiple of 4) bit[0]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[1]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[2]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[3]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[4]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[5]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[6]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[7]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[8]
(B1)
32-bit ring counter (2-phase multiple of 4) bit[9]
(B1)
32-bit ring counter (2-phase multiple of 4)
bit[10] (B1)
32-bit ring counter (2-phase multiple of 4)
bit[11] (B1)
32-bit ring counter (2-phase multiple of 4)
bit[12] (B1)
32-bit ring counter (2-phase multiple of 4)
bit[13] (B1)
32-bit ring counter (2-phase multiple of 4)
bit[14] (B1)
32-bit ring counter (2-phase multiple of 4)
bit[15] (B1)
User circuit logging mode is the
time division mode
A/D conversion value ch0[0] (E0)
A/D conversion value ch0[1] (E0)
A/D conversion value ch0[2] (E0)
A/D conversion value ch0[3] (E0)
A/D conversion value ch0[4] (E0)
A/D conversion value ch0[5] (E0)
A/D conversion value ch0[6] (E0)
A/D conversion value ch0[7] (E0)
A/D conversion value ch0[8] (E0)
A/D conversion value ch0[9] (E0)
A/D conversion value ch0[10] (E0)
A/D conversion value ch0[11] (E0)
A/D conversion value ch0[12] (E0)
A/D conversion value ch0[13] (E0)
A/D conversion value ch0[14] (E0)
A/D conversion value ch0[15] (E0)
Appendix 14 Logging Data Bit Assignment
A
APPX
719