User Circuit Block - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

User circuit block

The configuration of the user circuit block at the time of shipment from the factory is shown below.
User circuit block (uc2_top)
Digital signal
Digital input
[15:0] [15:0]
control part 0
(di2_top)
·
Digital signal
Digital input
[15:0] [95:80]
control part 5
(di2_top)
Digital signal [96]
Digital I/O
control part 0
(dio2_top)
·
[101]
Digital signal
Digital I/O
control part 5
(dio2_top)
Analog input
Analog signal
control part 0
(16bit×12ch)
(ai2_top)
·
Analog signal
Analog input
(16bit×12ch)
control part 2
(ai2_top)
Sampling pulse
Timing
generator
(tg2_top)
Internal block
Writing data
Register part
Constant write
(re2_top)
data
No. Function block
(1) Digital control part
(2) Logging control part
(3) Counter control part
(4) Pulse output part
(5) Analog output part
(6) Pulse generator
(7) Other connections
(1)
Digital signal
[101:0] Digital [101:0] [15:0]
control part
[15:0]
[95:80]
[95:80]
[96]
[96]
[101]
(4)
Pulse signal
[101]
[101:0]
Pulse
output part
Counter value (32 bits ×
6ch), phase A and phase
(3)
B inputs (2 bits × 6ch)
Counter [203:0]
control part
[395:204]
[779:588]
(6)
Pulse 1μs pulse output
generator
Internal block, 0-fixed output
Function
Inverts digital signals input from the digital input control part and digital input/output control part, and controls
output enable/disable.
Selects and outputs the logging data to be logged and the signal that controls the logging part. The logging control
part implements the following functions.
• Logging data selection
• Logging enable selection
• Logging end trigger selection
• User sampling pulse selection
Implements the following counters that operate with the signal from the digital input control part.
• 32-bit ring counter (2-phase multiple of 4)
• 32-bit ring counter (1-phase multiple of 1)
Outputs the following pulses to the digital output control part/digital input/output control part.
• 0 degree pulse
• 90 degree pulse
• 180 degree pulse
• 270 degree pulse
The pulse can be set in units of 10ns.
Generates the following DAC signals to be connected to the FPGA by register settings.
• D/A conversion value
• D/A conversion value enable
• LDAC
Generates a 1s pulse for logging data generation.
The following functions are implemented as other connections.
• HOLD/CLEAR of digital signals
• User interrupt output
• Connection control of various signals
Logging data
(2)
[779:0]
Logging
control
Logging enable
part
Logging trigger
User sampling pulse
(5)
[31:0]
Analog
output
[1:0]
part
[63:32]
[3:2]
[95:64]
[5:4]
10.1 FPGA Development Procedures
Digital output
control part 0
Digital signal[15:0]
(do2_top)
·
Digital output
control part 5
Digital signal[15:0]
(do2_top)
Digital I/O
Digital signal
control part 0
(dio2_top)
·
Digital signal
Digital I/O
control part 5
(dio2_top)
Logging data[431:0]
Logging part
Logging enable
(lf2_top)
Logging end trigger
User sampling pulse
Analog output data [31:0]
Analog output
[0] Analog output enable
control part 0
(ao2_top)
LDAC output [1:0]
Analog output data [31:0]
Analog output
[1] Analog output enable
control part 1
(ao2_top)
LDAC output [1:0]
Analog output data [31:0]
Analog output
[2] Analog output enable
control part 2
(ao2_top)
LDAC output [1:0]
Read data
Register part
(re2_top)
Constant read data
10 FPGA DEVELOPMENT
10
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