Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 601

Analog control data sampling pulse generation
■Address
Name
Analog control data sampling pulse generation (usr_wreg_1C8)
■Description
Outputs the data sampling of the analog input control part.
b15 b14 b13 b12
0 (fixed)
(1) Analog control data sampling pulse generation (B0)
• 1: Pulse output
• 0: No pulse output
(2) Analog control data sampling pulse generation (B1)
• 1: Pulse output
• 0: No pulse output
(3) Analog control data sampling pulse generation (B2)
• 1: Pulse output
• 0: No pulse output
(4) Analog control data sampling pulse generation (E0)
• 1: Pulse output
• 0: No pulse output
(5) Analog control data sampling pulse generation (E1)
• 1: Pulse output
• 0: No pulse output
(6) Analog control data sampling pulse generation (E2)
• 1: Pulse output
• 0: No pulse output
■FPGA initial value
0
■Firmware initial value

■Reset cause
Reset
■Precautions and restrictions
1 pulse is output by setting pulse output (1) to each bit. To output a pulse again, set to No pulse output (0)  Pulse output (1).
b11 b10 b9 b8 b7 b6 b5 b4
(6) (5)
FPGA register address
1000_B390H
b3 b2 b1 b0
(4) (3) (2) (1)
APPX
599
Appendix 4 FPGA register
A