Fpga Register Details (Analog Input Control Part) - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

FPGA register details (analog input control part)

A/D conversion enable/disable setting
■Address
Name
A/D conversion enable/disable setting (aiport_ad_start)
■Description
Enable or disable A/D conversion.
The firmware sets the A/D conversion enable/disable setting value to A/D conversion start as FPGA control start processing,
and A/D conversion starts. Therefore, A/D conversion start setting is not required.
b15 b14 b13 b12
0 (fixed)
(1) A/D conversion enable/disable setting (E0)
• 1: Conversion-enable
• 0: Conversion-disable
(2) A/D conversion enable/disable setting (E1)
• 1: Conversion-enable
• 0: Conversion-disable
(3) A/D conversion enable/disable setting (E2)
• 1: Conversion-enable
• 0: Conversion-disable
(4) A/D conversion start/stop setting
• 1: Start
• 0: Stop
(5) A/D conversion start/stop setting
• 1: Start
• 0: Stop
(6) A/D conversion start/stop setting
• 1: Start
• 0: Stop
■FPGA initial value
0
■Firmware initial value
0
■Reset cause
Reset
■Precautions and restrictions
When a DC I/O circuit board or Differential I/O circuit board is connected to E, the settings are disabled.
b11 b10 b9 b8 b7 b6 b5 b4
(6) (5) (4)
FPGA register address
1000_6000H
b3 b2 b1 b0
0 (3) (2) (1)
(fixed)
APPX
539
Appendix 4 FPGA register
A