Module Common Interface - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Module common interface

Logging control (output)
The timing chart when using the logging control (output) is shown below.
Ex.
If the FPGA register is set as follows:
FPGA register
Logging cycle timing (tim_log_cyc) (FPGA register address: 1000_2200H)
Logging data size setting (lgdw_area)(FPGA register address: 1000_9008H)
Set number of sampling after trigger (lower side) (lgdw_triggered_lsample) (FPGA register address:
1001_9000H)
Set number of sampling after trigger (upper side) (lgdw_triggered_usample) (FPGA register address:
1001_9002H)
Logging state register (lgdw_sts)(Address: 1000_9002H)
Number of samplings (lower) (lgdw_sample_lcount)(address: 1001_9004H)
Number of samplings (upper)(lgdw_sample_ucount)(address: 1001_9006H)
[User circuit block]
Logging data
uc_logdat_clk100m_reg[431:0]
Logging end trigger
uc_logend_clk100m_reg
Logging start (user circuit)
uc_logen_clk100m_reg
User sampling pulse
uc_loguserpulse_clk100m_reg
[Logging part]
DDR3L SDRAM
address generation
DDR3L SDRAM (External terminal output)
write processing
(1) Initialize the address (0000_0000H) at the start of logging.
(2) Issue a user sampling pulse from the user circuit block and write logging data to DDR3L SDRAM.
No. Description
1 Sets the internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) to Start(1).
2 Enables(1) the logging enable (uc_logen_clk100m_reg), and enables (1) the user sampling pulse (uc_loguserpulse_clk100m_reg).
3 Writes one record (data with time information (80 bits) and logging data (432 bits) as one unit) to DDR3L SDRAM.
■Storage operation mode (linear buffer mode)
3-1
Enables (1) the logging enable (uc_logen_clk100m_reg), and stops the operation when user sampling pulses are sent for the number of times set in
the logging data size setting (lgdw_area) (FPGA register address: 1000_9008H).
To perform logging again, it is necessary to set logging enable (uc_logen_clk100m_reg) from Enable (1) to Disable (0) and then Enable (1).
For DDR3L SDRAM sampling count (lower) (lgdw_sample_lcount) (FPGA register address: 1001_9004H) and number of samplings (upper)
(lgdw_sample_ucount) (FPGA register address: 1001_9006H), they are initialized when logging enable (uc_logen_clk100m_reg) is set to Enable (1H).
3-2 ■Storage operation mode (ring buffer mode)
Enables (1) Logging enable (uc_logen_clk100m_reg), and initializes the DDR3L SDRAM address to 0000_0000H when user sampling pulses are sent
for the number of times set in the logging data size setting (lgdw_area) (FPGA register address: 1000_9008H).
To stop logging, set logging enable (uc_logen_clk100m_reg) to Disable (0).
To perform logging again, it is necessary to set logging enable (uc_logen_clk100m_reg) to Enable (1).
For DDR3L SDRAM sampling count (lower) (lgdw_sample_lcount)(FPGA register address: 1001_9004H) and number of samplings (upper)
(lgdw_sample_ucount) (FPGA register address: 1001_9006H), they are initialized when logging enable (uc_logen_clk100m_reg) is set to Enable (1H).
■In trigger operation mode
3-3
If the logging end trigger is enabled while operating in the storage operation mode (ring buffer mode), the operation will stop when logging data is sent
for the number of times set in the post-trigger sampling count.
To perform logging again, it is necessary to set Logging enable (uc_logen_clk100m_reg) from Enable (1) to Disable (0) and then Enable(1).
For DDR3L SDRAM sampling count (lower) (lgdw_sample_lcount)(FPGA register address: 1001_9004H) and number of samplings (upper)
(lgdw_sample_ucount) (FPGA register address: 1001_9006H), they are initialized when logging enable (uc_logen_clk100m_reg) is set to Enable (1H).
11 FPGA INTERNAL CIRCUIT
220
11.4 User Circuit Block
(O) Logging data M
(O) L
(O) L
(O) L
(1)
Address (Initialization:
(Internal)
0000_0000H)
Logging data M + 1 Logging data M + 2
Cycle (minimum 1μs)
DDR3L SDRAM write processing
(logging data M + 1, address 0000_0000H)
(2)
Setting Remarks
value
0001H 1s
0H 256 records (16kB)
0200H 512
0H

For monitoring logging status

For monitoring the number of
times logged

Logging data M + 3
Address + 1
DDR3L SDRAM write processing
(logging data M + 2, address + 1)