Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 266

Cc-link ie tsn fpga module

Table of Contents

■Counter control (32-bit ring counter (2-phase multiple of 4))

It detects the rising edge and falling edge of Phase A and Phase B, and outputs the counter UP and DOWN signals in one

pulse (clk100m). The truth table of the UP output and DOWN output is shown below.

1b (disable)

Except for that shown above

■Counter (32 bits)

The truth table of the 32-bit counter is shown below. Ring/Linear is input as a ring-fixed value, and the counter lower limit

value is input as a 0000_0000h fixed value.

1b (disable)

The 32-bit counter is used in common for the 32-bit ring counter (2-phase multiple of 4) and the 32-bit ring

counter (1-phase multiple of 1).

■Counter control (32-bit ring counter (1-phase multiple of 1))

It detects the rising edge of Phase A and Phase Z, and outputs the UP signal and DOWN signal in one pulse. The truth table

of the UP/DOWN output is shown below.

1b (disable)

11 FPGA INTERNAL CIRCUIT

11.4 User Circuit Block

0b (disable)

UP_LIM[31:0]

0b (disable)

COUNT=UP_LIM-1

Except for that

COUNT=UP_LIM

Except for that

0b (disable)

DOWN_LIM[31:0]

COUNT=DOWN_LIM

Except for that shown

COUNT=DOWN_LIM

Except for that shown

Troubleshooting