Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 616

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
APPX
614
Appendix 5 List of User Circuit Block Terminals
Terminal
signal Signal name
re_rs_usr_wreg_0 Write data 35
23_clk100m_reg
re_rs_usr_wreg_0 Write data 36
24_clk100m_reg
re_rs_usr_wreg_0 Write data 37
25_clk100m_reg
re_rs_usr_wreg_0 Write data 38
26_clk100m_reg
re_rs_usr_wreg_0 Write data 39
27_clk100m_reg
re_rs_usr_wreg_0 Write data 40
28_clk100m_reg
re_rs_usr_wreg_0 Write data 41
29_clk100m_reg
re_rs_usr_wreg_0 Write data 42
2a_clk100m_reg
re_rs_usr_wreg_0 Write data 43
2b_clk100m_reg
re_rs_usr_wreg_0 Write data 44
2c_clk100m_reg
re_rs_usr_wreg_0 Write data 45
2d_clk100m_reg
re_rs_usr_wreg_0 Write data 46
2e_clk100m_reg
re_rs_usr_wreg_0 Write data 47
2f_clk100m_reg
re_rs_usr_wreg_0 Write data 48
30_clk100m_reg
re_rs_usr_wreg_0 Write data 49
31_clk100m_reg
re_rs_usr_wreg_0 Write data 50
32_clk100m_reg
re_rs_usr_wreg_0 Write data 51
33_clk100m_reg
re_rs_usr_wreg_0 Write data 52
34_clk100m_reg
re_rs_usr_wreg_0 Write data 53
35_clk100m_reg
re_rs_usr_wreg_0 Write data 54
36_clk100m_reg
re_rs_usr_wreg_0 Write data 55
37_clk100m_reg
re_rs_usr_wreg_0 Write data 56
38_clk100m_reg
re_rs_usr_wreg_0 Write data 57
39_clk100m_reg
re_rs_usr_wreg_0 Write data 58
3a_clk100m_reg
re_rs_usr_wreg_0 Write data 59
3b_clk100m_reg
re_rs_usr_wreg_0 Write data 60
3c_clk100m_reg
re_rs_usr_wreg_0 Write data 61
3d_clk100m_reg
re_rs_usr_wreg_0 Write data 62
3e_clk100m_reg
re_rs_usr_wreg_0 Write data 63
3f_clk100m_reg
Bit Input/ Polarity
width output

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input

16 Input

16 Input
16 Input 

16 Input

16 Input

16 Input
Initial 1shot Sync clock
value
Feq

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
0000H  100MHz

0000H 100MHz

0000H 100MHz

0000H 100MHz
Clock
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m
clk100m