Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 671

Connec- Ter- Exter- Each
tion cir- minal nal ter- circuit
cuit num- minal board
board ber name func-
tion ter-
minal
name
DC I/O M25 IOE0_Y2 IOE0_Y[2
circuit ]
board
Differential IOE0_DO
I/O circuit 422[2]
board
Analog I/O IOE0_DA
circuit _SCLK
board
DC I/O M24 IOE0_Y3 IOE0_Y[3
circuit ]
board
Differential IOE0_DO
I/O circuit 422[3]
board
Analog I/O IOE0_DA
circuit _SDI
board
DC I/O M22 IOE0_Y4 IOE0_Y[4
circuit ]
board
Differential IOE0_DO
I/O circuit 422[4]
board
Analog I/O IOE0_DA
circuit _SYNCL
board
DC I/O M21 IOE0_Y5 IOE0_Y[5
circuit ]
board
Differential IOE0_DO
I/O circuit 422[5]
board
Analog I/O IOE0_DA
circuit _SDO
board
DC I/O N25 IOE0_Y6 IOE0_Y[6
circuit ]
board
Differential IOE0_DO
I/O circuit 422[6]
board
Analog I/O IOE0_DA
circuit _LDACL[
board 0]
Func- I/O di- I/O di- I/O
tions rec- rec- type
tion tion
for
each
cir-
cuit
board
DC output Output Output 3.3-V
[2] LVCM
OS
Differential
(RS-422)
output [2]
DAC serial
clock
output
(common
to 2 chips)
DC output Output Output 3.3-V
[3] LVCM
OS
Differential
(RS-422)
output [3]
DAC serial
data
output
(common
to 2 chips)
DC output Output Output 3.3-V
[4] LVCM
OS
Differential
(RS-422)
output [4]
DAC sync
output
(common
to 2 chips)
DC output Output Output 3.3-V
[5] LVCM
OS
Differential
(RS-422)
output [5]
DAC serial
data input
(reserved)
DC output Output Output 3.3-V
[6] LVCM
OS
Differential
(RS-422)
output [6]
DACLDAC
signal
output
I/O Logic PU/ Initial state
volt- PD in
Re-
age FPGA
set-
ting

3.3V PU H
3.3V  PU H

3.3V PU H
Negative
3.3V  PU H

3.3V PU H
Positive
Appendix 6 A List of FPGA External Terminals
Operating
frequency
After
reset
re-
lease
L 25MHz
H 4.17MHz
L 25MHz
L 25MHz
H 4.17MHz
L 12.5MHz
L 25MHz
A
H 4.17MHz
12.5MHz
L 25MHz
H 4.17MHz

L 25MHz
H 4.17MHz
L 12.5MHz
APPX
669