Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 516

FPGA Register
register name
address
1000_B258H usr_wreg_12C
1000_B260H usr_wreg_130
1000_B262H usr_wreg_131
1000_B264H usr_wreg_132
1000_B266H usr_wreg_133
1000_B268H usr_wreg_134
1000_B26AH usr_wreg_135
1000_B26CH usr_wreg_136
1000_B26EH usr_wreg_137
1000_B270H usr_wreg_138
1000_B272H usr_wreg_139
1000_B274H usr_wreg_13A
1000_B276H usr_wreg_13B
1000_B278H usr_wreg_13C
1000_B27AH usr_wreg_13D
1000_B27CH usr_wreg_13E
1000_B27EH usr_wreg_13F
1000_B280H usr_wreg_140
1000_B282H usr_wreg_141
1000_B284H usr_wreg_142
1000_B286H usr_wreg_143
1000_B288H usr_wreg_144
1000_B28AH usr_wreg_145
1000_B28CH usr_wreg_146
1000_B28EH usr_wreg_147
1000_B290H usr_wreg_148
1000_B292H usr_wreg_149
1000_B294H usr_wreg_14A
1000_B296H usr_wreg_14B
1000_B298H usr_wreg_14C
1000_B29AH usr_wreg_14D
1000_B2C0H usr_wreg_160
1000_B2D0H usr_wreg_168
1000_B2FEH usr_wreg_17F
1000_B300H usr_wreg_180
1000_B302H usr_wreg_181
1000_B310H usr_wreg_188
1000_B312H usr_wreg_189
1000_B314H usr_wreg_18A
1000_B316H usr_wreg_18B
1000_B318H usr_wreg_18C
1000_B31AH usr_wreg_18D
1000_B31CH usr_wreg_18E
1000_B31EH usr_wreg_18F
1000_B320H usr_wreg_190
APPX
514
Appendix 4 FPGA register
Description
Pulse output part output pulse count upper limit value (upper side) (E2)
Pulse output part pulse output selection 0 (B0)
Pulse output part pulse output selection 1 (B0)
Pulse output part pulse output selection 2 (B0)
Pulse output part pulse output selection 0 (B1)
Pulse output part pulse output selection 1 (B1)
Pulse output part pulse output selection 2 (B1)
Pulse output part pulse output selection 0 (B2)
Pulse output part pulse output selection 1 (B2)
Pulse output part pulse output selection 2 (B2)
Pulse output part pulse output selection 0 (E0)
Pulse output part pulse output selection 1 (E0)
Pulse output part pulse output selection 2 (E0)
Pulse output part pulse output selection 0 (E1)
Pulse output part pulse output selection 1 (E1)
Pulse output part pulse output selection 2 (E1)
Pulse output part pulse output selection 0 (E2)
Pulse output part pulse output selection 1 (E2)
Pulse output part pulse output selection 2 (E2)
Pulse output part pulse output mask 0 (B0)
Pulse output part pulse output mask 1 (B0)
Pulse output part pulse output mask 0 (B1)
Pulse output part pulse output mask 1 (B1)
Pulse output part pulse output mask 0 (B2)
Pulse output part pulse output mask 1 (B2)
Pulse output part pulse output mask 0 (E0)
Pulse output part pulse output mask 1 (E0)
Pulse output part pulse output mask 0 (E1)
Pulse output part pulse output mask 1 (E1)
Pulse output part pulse output mask 0 (E2)
Pulse output part pulse output mask 1 (E2)
Analog output part LDAC output selection
Analog output part HOLD/CLEAR
Test mode setting
Logging control part user logging control
Logging control part 1 enable clear
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction
(B0)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower
side) (B0)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper
side) (B0)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction
(B1)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower
side) (B1)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper
side) (B1)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset instruction
(B2)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (lower
side) (B2)
Counter control part 32-bit ring counter (2-phase multiple of 4) preset data (upper
side) (B2)
Type Read Write
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