Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 629

Connection destination
Block name Instance
name
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Register part u_re2_top
Terminal
signal Signal name
re_rs_usr_wreg_1 Write data 412
9c_clk100m_reg
re_rs_usr_wreg_1 Write data 413
9d_clk100m_reg
re_rs_usr_wreg_1 Write data 414
9e_clk100m_reg
re_rs_usr_wreg_1 Write data 415
9f_clk100m_reg
re_rs_usr_wreg_1 Write data 416
a0_clk100m_reg
re_rs_usr_wreg_1 Write data 417
a1_clk100m_reg
re_rs_usr_wreg_1 Write data 418
a2_clk100m_reg
re_rs_usr_wreg_1 Write data 419
a3_clk100m_reg
re_rs_usr_wreg_1 Write data 420
a4_clk100m_reg
re_rs_usr_wreg_1 Write data 421
a5_clk100m_reg
re_rs_usr_wreg_1 Write data 422
a6_clk100m_reg
re_rs_usr_wreg_1 Write data 423
a7_clk100m_reg
re_rs_usr_wreg_1 Write data 424
a8_clk100m_reg
re_rs_usr_wreg_1 Write data 425
a9_clk100m_reg
re_rs_usr_wreg_1 Write data 426
aa_clk100m_reg
re_rs_usr_wreg_1 Write data 427
ab_clk100m_reg
re_rs_usr_wreg_1 Write data 428
ac_clk100m_reg
re_rs_usr_wreg_1 Write data 429
ad_clk100m_reg
re_rs_usr_wreg_1 Write data 430
ae_clk100m_reg
re_rs_usr_wreg_1 Write data 431
af_clk100m_reg
re_rs_usr_wreg_1 Write data 432
b0_clk100m_reg
re_rs_usr_wreg_1 Write data 433
b1_clk100m_reg
re_rs_usr_wreg_1 Write data 434
b2_clk100m_reg
re_rs_usr_wreg_1 Write data 435
b3_clk100m_reg
re_rs_usr_wreg_1 Write data 436
b4_clk100m_reg
re_rs_usr_wreg_1 Write data 437
b5_clk100m_reg
re_rs_usr_wreg_1 Write data 438
b6_clk100m_reg
re_rs_usr_wreg_1 Write data 439
b7_clk100m_reg
re_rs_usr_wreg_1 Write data 440
b8_clk100m_reg
Bit Input/ Polarity Initial
width output value

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H

16 Input 0000H

16 Input 0000H
16 Input  0000H

16 Input 0000H
16 Input  0000H
Appendix 5 List of User Circuit Block Terminals
1shot Sync clock
Feq Clock

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m

100MHz clk100m

100MHz clk100m
 100MHz clk100m

100MHz clk100m
 100MHz clk100m
APPX
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