Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 540

Cc-link ie tsn fpga module

Table of Contents

Differential output HOLD/CLEAR

Differential output HOLD/CLEAR (IOB0_DIO485_O) (B0) (ioport_iob0y_holdclr)

Differential output HOLD/CLEAR (IOB1_DIO485_O) (B1) (ioport_iob1y_holdclr)

Differential output HOLD/CLEAR (IOB2_DIO485_O) (B2) (ioport_iob2y_holdclr)

Differential output HOLD/CLEAR (IOE0_DIO485_O) (E0) (ioport_ioe0y_holdclr)

Differential output HOLD/CLEAR (IOE1_DIO485_O) (E1) (ioport_ioe1y_holdclr)

Differential output HOLD/CLEAR (IOE2_DIO485_O) (E2) (ioport_ioe2y_holdclr)

■Description

When the internal operation start/stop (mode_ctrl2) is stopped (0), the logic of the output signal (IOB_DIO485_O) or the

output signal (IOE_DIO485_O) is fixed.

• 2H, 3H: HOLD (previous value held)

• 1H: CLEAR (fixed to H)

• 0H: CLEAR (fixed to L)

■FPGA initial value

■Firmware initial value

■Reset cause

■Precautions and restrictions

• Changes to this register when b0 of internal operation start/stop (mode_ctrl2) (FPGA register address: 1000_0002H) is

stopped (0) are immediately reflected.

• If the external reset ON/OFF setting (ioport_set) is reset ON (0), the differential output circuit outside the FPGA is reset.

Therefore, the logic of the output signals (IOB_Y0 to IOB_Y7) set by the differential output HOLD/CLEAR to the output

signals (IOB_Y0 to IOB_Y7) after output signal selection (after selection by the oport_iob0y_osel register), or output

signals (IOE_Y0 to IOE_Y7) to the output signals (IOE_Y0 to IOE_Y7) after output signal selection (after selection

by the oport_ioe0y_osel register) is not output outside the module.

• When a DC I/O circuit board is connected to B or E, the settings are disabled.

• When an analog I/O circuit board is connected to E, the settings are disabled.

Appendix 4 FPGA register

FPGA register address

Troubleshooting