Table of Contents
Advertisement
Appendix 8
The processing time of CC-Link IE TSN is the time until the device operation of the master station CPU module is reflected in
the FPGA register, or the time until the state of FPGA register is reflected in the device of the master station CPU module. The
CC-Link IE TSN processing time is determined by the following processing time.
• CC-Link IE TSN processing time = cyclic transmission delay time + remote station processing time
Transmission delay time of cyclic transmission ( User's manual of the master station used)
Remote station processing time: 1ms
APPX
682
Appendix 8 CC-Link IE TSN Processing Time
CC-Link IE TSN Processing Time
Advertisement
Table of Contents
Troubleshooting
