Chapter 21 Troubleshooting During Fpga Development - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

21
TROUBLESHOOTING DURING FPGA
DEVELOPMENT
This section shows troubleshooting during FPGA development. Troubleshooting during FPGA development is performed
when the FPGA does not operate normally even though normal signals are being input to the FPGA.
When unintended behavior occurs during actual device verification
When unintended behavior occurs during actual device verification, check the following items.
Check item
Has the standard circuit been changed?
Is there any problem with FPGA design and verification?
Has the FPGA logic synthesis environment been
changed?
Has the FPGA pin assignment been changed?
Does Timing Violation occur in the standard circuit during
FPGA logic synthesis?
Does Timing Violation occur in the user circuit during
FPGA logic synthesis?
Did a Warning/Error occur during FPGA logic synthesis?
Are there any problems with the parameter settings for
actual device verification?
Action
Using a difference check tool, check if there are any differences between the RTL downloaded from
the Mitsubishi Electric FA site and the RTL for which FPGA logic synthesis is performed.
Please review the FPGA design/verification performed by the customer. Confirm that the following
precautions are observed.
 4.5.2.2. User circuit, (4) User circuit (I/F specifications) notes/restrictions
Check if the configuration file for the logic synthesis environment in Table 3.7-21 has not been
changed.
Check that the report file (top.pin) after FPGA logic synthesis matches the result of logic synthesis
with RTL downloaded from the Mitsubishi Electric FA site.
Please review the points shown below in the RTL (uc2_top.v) modified by the customer.
• Circuit scale
• Interface of uc2_top.v
• Number of flip-flop fan-outs
Please review the points shown below in the RTL (uc2_top.v) created by the customer.
• Circuit scale
• Amount of delay between flip-flops
• Timing restriction file
Check the FPGA logic synthesis result.
Check if the same parameters as used in FPGA design/verification are set. If there are no problems
with the parameter settings, check the operation of the actual device using the Signal Tap logic
analyzer that is included in the FPGA development software. For instructions on how to use the
tools that are included in the FPGA development software, please contact the Intel
21 TROUBLESHOOTING DURING FPGA DEVELOPMENT
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