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Reset system diagram
The reset system diagram is shown below.
DDR3L
SDRAM
Micro-
computer
Configuration data I/F
Configuration ROM
RSTL
Reset
Oscillator
circuit
Internal operation start/stop
Reset
*1 IOB1_RSTL, IOB2_RSTL, and IOE_RSTL have the same structure.
For details on the reset system, refer to the following.
Page 188 Reset control part (rc2_top)
Top part (top1)
(5)
Platform part
(pt2_top)
(6)
(4)
Logging part
DDR3L SDRAM
(lf2_top)
control part
(dc3_top)
FIFO
IP
(3)
Microcomputer
I/F part
(mi3_top)
(14)
Register part (re2_top)
(1)
Reset control
part (rc2_top)
(2)
Clock control
PLL_LOCK
part (cc2_top)
Internal operation clock
PLL
(100MHz)
FPGA internal FF (excluding the
DDR3 SDRAM control part)
(7)
Timing generator
(tg2_top)
I/O control block
(8)
Digital input control
User circuit
part (di2_top)
block
(uc2_top)
Digital filter
(9)
Digital output control
part (do2_top)
(10)
Digital I/O control part
(dio2_top)
Digital filter
(11)
Analog input control
part (ai2_top)
ADC initialization
(12)
Analog output control
part (ao2_top)
DAC initialization
WDT error
All FFs in the
FPGA
(7), (8), (9), (10),
(11), (12), (15)
11 FPGA INTERNAL CIRCUIT
(13)
I/O
selector
(is2_top)
Connector
Connector
Connector
Connector
1'b0
*1
IOB0_RSTL
1'b0
11.1 Overview
11
B0
B1
B2
E0
E1
E2
185
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