Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 110

■NZ2EX2S-D41D01
Item
Reset control External reset ON/OFF
part setting
Timing control Data sampling timing
part setting
Filter sampling pulse
Data update timing
Logging cycle timing
Digital input Input filter upper limit
control part value X0 to Input filter
setting upper limit value X7
Digital output Output signal selection
control part Y0 to Output signal
setting selection Y7
Differential output HOLD/
CLEAR Y0 to Differential
output HOLD/CLEAR
*4
Y7
Digital I/O Select output signal or I/O
control part direction signal
setting
I/O direction setting
Input filter upper limit
value
Differential output HOLD/
CLEAR
Analog input A/D conversion enable/
control part disable setting
setting
ADC range setting CH0 to
ADC range setting CHB
ADC offset value CH0 to
ADC offset value CHB
Select A/D conversion
timing
ADC oversampling ratio
setting
8 FPGA MODULE CONFIGURATION TOOL
108
8.6 Parameter Setting Function
Description
Sets ON/OFF of the reset issued to the
board when FPGA control is stopped.
Sets the timing (cycle) for sampling
differential (RS-422/RS-485) input and
analog input.
Sets the operation cycle of the digital filter.
The data sampling timing cannot be set for
the differential I/O board. The same value
as this setting is set for the data sampling
timing.
Sets the output timing (cycle) for differential
(RS-422/RS-485) output.
*1
Sets the logging cycle.
Sets the filter upper limit value of the
differential (RS-422) input digital filter.
*2
Sets the signal output to the differential
(RS-422) output.
*3
Sets the differential (RS-422) output value
when FPGA control is stopped for a
differential I/O board.
Select the input/output direction signal.
*5
When "Select output signal or I/O direction
signal" is set to "Register setting value (RY
or I/O direction)", this item sets the input
and output direction of differential (RS-485)
input/output.
Sets the filter upper limit value of the
differential (RS-485) input digital filter.
When "External reset ON/OFF" is set to
*6
"OFF" and "Select output signal or I/O
direction signal" is set to "User circuit
output", this sets the differential (RS-485)
output value when FPGA control is
stopped.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
It is masked and cannot be set.
Setting range
• ON
• OFF
0.01 to 0.01s
• 0.01s
• 0.02s
• 0.04s
• 0.08s
• 0.10s
• 0.14s
• 0.16s
• 0.20s
• 0.32s
• 0.40s
• 0.50s
• 1.00s
• 2.00s
• 10.00s
• 100.00s
0.01s to 655.36s (set in units of
0.01s)
1s to 32768s (set in units of 1s)
0 to 4095
• Register setting value (RY)
• User circuit output
• CLEAR (fixed to L)
• CLEAR (fixed to H)
• HOLD
• Register setting value (RY or I/O
direction)
• User circuit output
• Input
• Output
0 to 4095
• CLEAR (fixed to L)
• CLEAR (fixed to H)
• HOLD
Default
ON
0.01s
0.01s
0.01s
1s
1500
Register setting
value (RY)
CLEAR (fixed to H)
Register setting
value (RY or I/O
direction)
Input
1500
CLEAR (fixed to H)
Conversion-disable
-9.9V to 9.9V
0
Data sampling
timing
No setting