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7.1NITIAL SETTING OF TRANSMISSION CONTROL
DATA TO BUFFER MEMORY
MELSEC-A
7.10
Reading the Transmission Specification Settingswitch Statuses
This section describes the reading of the statuses of the transmission
specification setting switches on the face of the AJ71 UC24, stored in the
buffer.
(1) Switch status indicating area
The statuses of the transmission specification setting switches are
stored in buffer memory address I IFH, as illustrated below.
-
SW11: Main channel setting
I
1
1 1
1
: ;
bit
setting
SW14: Transmission speed setting
SW16: Parity bit presencelabsence setting
SW17: EvenIOdd parity setting
SW18: Stop bit setting
SW21: Sum check enableldisable setting
SW22: Write during RUN enableldisable setting
SW23: Computer linwmultidrop link selection
SW24: Unused
I
The
SW23 must be set to 1.
I
(2) Example of a program for reading the switch status indicating area
The following is an example of a program for reading the statuses of the
transmission s~ecification setting switches stored in buffer memory
.
address 11 FH.
Example of program (AJ71 UC24 I10 addresses 80 to 9F)
The data stored in the switch status indicating
H
ti
F R O M P l - H
area is read to D20.
,
,
I
I
l
l
l
l
1
L---
8-bit
I I I I I I
LA-----
I
2400(BPS)
I i ; i i L
--------
Parity bit present
,
1
1
1
-
Even parity
I
I
I
L
I-bit
b15to b12 b l l b10 b9 b8 b7
b6
b5 b4 b 3 b2 b l W
I
I
L
-----------
L
Sum check enabled
L
- - -
-
- -
- -
-
- - -
Write during RUN disabled
- -
- -
-
- - - - - - - -
Computer link
piiq
For the data of each bit in the switch status indicating area depends on the settings of the
transmission specification setting switches on the face of the AJ71UC24 (see Section 4.3.2).
11FH
0
1
0
1
0
1
t
O
1
1
1
0
I I I I I I
I
I
I
I
I
I
I
I I
I
I
L--
RS-232C
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