Clock System Diagram; Fpga External Terminal List; Fpga Memory Map; Register - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Clock system diagram

The clock system diagram is shown below.
DDR3L
SDRAM
Micro-
computer
Configuration data I/F
Configuration ROM
Oscillator
circuit
For details on the clock system, refer to the following.
Page 189 Clock control part (cc2_top)

FPGA external terminal list

For the list of FPGA external terminals, refer to the following. In addition, the external terminal connected to the connector
recognizes the connected circuit board type inside the FPGA and automatically connects to the appropriate block.
Page 651 A List of FPGA External Terminals

FPGA memory map

For the FPGA memory map, refer to the following.
Page 321 FPGA Register Access Function

Register

For details on the FPGA, refer to the following.
Page 502 FPGA register
11 FPGA INTERNAL CIRCUIT
186
11.1 Overview
Top part (top1)
(5)
Platform part
(pt2_top)
(6)
(4)
Logging part
DDR3L SDRAM
(lf2_top)
control part
(dc3_top)
FIFO
PLL
IP
(3)
Microcomputer
I/F part
(mi3_top)
(14)
Register part
(re2_top)
(1)
Reset control
part (rc2_top)
(2)
Clock control PLL_LOCK
part (cc2_top)
Internal operation clock Internal operation clock
PLL
(100MHz) (100MHz)
FPGA internal FF FPGA internal FF
(excluding the DDR3 SDRAM control part) (excluding the DDR3 SDRAM control part)
(7)
Timing generator
(tg2_top)
I/O control block
(8)
Digital input control
User circuit
part (di2_top)
block
(uc2_top)
Digital filter
(9)
Digital output control
part (do2_top)
(10)
Digital I/O control part
(dio2_top)
Digital filter
(11)
Analog input control
part (ai2_top)
ADC initialization
(12)
Analog output control
part (ao2_top)
DAC initialization
(13)
I/O
selector
(is2_top)
Connector Connector B0 B0
Connector Connector B1 B1
Connector Connector B2 B2
Connector Connector
E0 E0
E1 E1
E2 E2