Mitsubishi Electric NZ2GN2S-D41P01 User Manual page 155

4.
To check B0, set the register areas as shown in the table below. Also set b0 of Write/read data control register
(usr_wrdat_ctrl) (FPGA register address: 1000_A000H) to 1.
Register name
Output signal/Input output direction signal selection (B0)
(ioport_iob0_dio485_osel)
Digital input/output control digital output selection (usr_wreg_086)
Digital input/output control input/output control register (B0)
(usr_wreg_080)
5.
After starting the internal operation, input 1 for 0.5s and then 0 for 0.5s to IOB0_DIO485_I.
When the internal operation is set to Stop, IOB0-2_RSTL/IOE_RSTL becomes 0. When it is set to Start, IOB0-2_RSTL/
IOE_RSTL becomes 1.
Check that 0 is output from IOB0_DIO485_O and IOB0_DIO485_EN.
6.
Switch the setting value of the Digital input/output control input/output control register according to the table in step 4,
and then perform step 5.
Check that the following values are output.
If the setting value is 0001H, check that the input value from IOB0_DIO485_O to IOB0_DIO485_I is output and 0 is output
from IOB0_DIO485_EN. If the setting value is 0003H, check that the inverted input value from IOB0_DIO485_O to
IOB0_DIO485_I is output and 0 is output from IOB0_DIO485_EN. If the setting value is 0005H, check that the input value
from IOB0_DIO485_O to IOB0_DIO485_I is output and 1 is output from IOB0_DIO485_EN.
7.
Read B0 as B1, B2, and E0 to E2 and perform steps 4 to 6.
Check that the values are output where each value is obtained by replacing B0 in steps 5 and 6 with B1, B2, and E0 to E2.
Setting value
0003H
003EH001FH
0000H0001H0003H0005H
Reference
Page 536 Select output signal or I/O
direction signal
Page 578 Digital I/O control digital output
selection
Page 577 Digital I/O control I/O control
register
10 FPGA DEVELOPMENT
10.3 FPGA Verification Procedure
10
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