Standard Circuit; Module Common Circuit - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Cc-link ie tsn fpga module

Table of Contents

Standard Circuit

Do not change the standard circuit. If the standard circuit is modified, the operation of various functions cannot be guaranteed.

Reset control part (rc2_top)

All register areas inside the FPGA are reset by a reset (RSTL) input from the MCU until the state transition of the FPGA or

module is established, such as during configuration. In addition, the circuit in the FPGA can be started/stopped at any timing

on the program.

TOP part (top1)

Clock control

part (cc2_top)

Reset signal

The reset is output as is for the PLL. (rst_hw_n: Reset (for PLL))

Also, for other resets (rst_n: system reset, rst_ddr_n: DDR3L SDRAM IF reset), the status remains as reset during the PLL

unlock period.

PLL lock signal

Reset (for PLL)

System reset

FPGA external terminal

Internal operation

 After the reset is released, the inside of the FPGA is reset (rst_re_hw_n=0, rst_n=0) during the PLL lock period.

 After the reset inside the FPGA, the connection of the external terminal is switched according to the type of circuit board to be connected.

 DDR3L SDRAM calibration is executed and the end of calibration is notified to the MCU.

 When the MCU sets internal operation start/stop to Start(1), the internal operation of the FPGA is started.

11 FPGA INTERNAL CIRCUIT

11.3 Standard Circuit

Reset control part

System reset

Reset for DDR3L SDRAM IF

Reset (for PLL))

PLL lock period

FPGA activation signal generation

Other than DDR3L SDRAM IF

DDR3L SDRAM IF

FPGA external terminal connection completed

Calibration completed