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10.4
FPGA Logic Synthesis Procedures
Logic synthesis environment
The logic synthesis environment for the provided sample circuit is shown below. Modify this environment and execute logic
synthesis.
: Need to be changed according to the user circuit block, : Do not change
No.
Directory
(1)
$HOME
(2)
RTL
(3)
(4)
(5)
(6)
Layout
(7)
(8)
(9)
(10)
(11)
(12)
SAMPLE_CONFIGURATION
_DATA
(13)
(14)
(15)
10 FPGA DEVELOPMENT
174
10.4 FPGA Logic Synthesis Procedures
Description
Logic synthesis top folder
RTL storage directory
TOP
RTL storage directory (top layer)
UC
RTL storage directory (UC) (user circuit block)
*/
RTL storage directory (TOP, each block) (standard circuit)
Logic synthesis folder
top.qpf
Project file for the FPGA development software
top.qsf
Restrictions file for the FPGA development software
top.sdc
Restrictions file for logic synthesis
top_jtag.sdc
Restrictions file for logic synthesis (for JTAG)
conv_.cof
jic file, rpd file generation script
Storage directory for sample configuration data
top_compressed.jic
Sample configuration data file (JIC format)
top_compressed.rpd
Sample configuration data file (RPD format)
top.sof
Sample configuration data file (SOF format)
Changeability
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