Function Blocks - Mitsubishi Electric NZ2GN2S-D41P01 User Manual

Function blocks

Standard circuit
Do not change the standard circuit. If the standard circuit is modified, the operation of various functions cannot be guaranteed.
DDR3L
SDRAM
Micro-
computer
Configuration data I/F
Configuration ROM
Oscillator
circuit
No. Function blocks
(1) Reset control part
(2) Clock control part
(3) Microcomputer I/F
part
(4) DDR3L SDRAM
control part
(5) Platform part
11 FPGA INTERNAL CIRCUIT
182
11.1 Overview
Top part (top1)
(5)
Platform part
(pt2_top)
(6)
(4)
Logging part
DDR3L SDRAM
(lf2_top)
control part
(dc3_top)
FIFO
IP
(3)
Microcomputer
I/F part
(mi3_top)
(14)
Register part (re2_top)
(1)
Reset control
part (rc2_top)
(2)
Clock control
PLL_LOCK
part (cc2_top)
Internal operation clock
PLL (100MHz)
Function
Controls the reset inside the FPGA.
The reset from the MCU is connected to all register areas in the
FPGA.
Generates the system clock used inside the FPGA. The system clock
is 100MHz.
Controls register access/memory access from the MCU. It controls
the 16-bit data bus.
Writes the logging data output from the logging block to DDR3L
SDRAM. In addition, logging data is read from DDR3L SDRAM by a
read request from the microcomputer I/F part
 
Implements Intel FPGA Avalon
inside the FPGA and the microcomputer I/F part. FPGA internal CPU

(Nios /e) is equipped with a program ROM, WorkRAM, and
DPRAM for output value storage as peripheral circuits. The following
functions are implemented in the platform part.
• Controls writing of logging data to DDR3L SDRAM.

• Microcomputer I/F part, Nios
DDR3L SDRAM.
User circuit block
(uc2_top)
FPGA internal FF
(excluding the DDR3 SDRAM control part)
interface and connects the IP
/e controls reading/writing to
(7)
Timing generator
(tg2_top)
(13)
I/O control block
I/O
selector
(8)
(is2_top)
Digital input control
part (di2_top)
Digital filter
(9)
Digital output control
part (do2_top)
(10)
Digital I/O control part
(dio2_top)
Digital filter
(11)
Analog input control
part (ai2_top)
ADC initialization
(12)
Analog output control
part (ao2_top)
DAC initialization
Classification Reference
Module common Page 188 Reset control
circuit part (rc2_top)
Module common Page 189 Clock control
circuit part (cc2_top)
Module common Page 190 Platform part
circuit (pt2_top)
Module common
circuit
Module common
circuit
Connector B0
B1
Connector
Connector B2
Connector
E0
E1
E2