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Connection destination
Block name
Instance
name
Digital I/O
u_dio2_top_e0
control part
Digital I/O
u_dio2_top_e0
control part
Digital I/O
u_dio2_top_e1
control part
Digital I/O
u_dio2_top_e1
control part
Digital I/O
u_dio2_top_e2
control part
Digital I/O
u_dio2_top_e2
control part
Analog output
u_ao2_top_e0
control part
Analog output
u_ao2_top_e0
control part
Analog output
u_ao2_top_e0
control part
Analog output
u_ao2_top_e1
control part
Analog output
u_ao2_top_e1
control part
Analog output
u_ao2_top_e1
control part
Analog output
u_ao2_top_e2
control part
Analog output
u_ao2_top_e2
control part
Analog output
u_ao2_top_e2
control part
Logging part
u_lf2_top
Logging part
u_lf2_top
Logging part
u_lf2_top
Logging part
u_lf2_top
Register part
u_re2_top
FPGA external
top1
Analog input
u_ai2_top_e0,
control part
u_ai2_top_e1,
u_ai2_top_e2
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Register part
u_re2_top
Terminal
signal
Signal name
uc_ioe0_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
E0)
uc_ioe0_dio485_e
Digital I/O control
n_clk100m_reg
(E0)
uc_ioe1_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
E1)
uc_ioe1_dio485_e
Digital I/O control
n_clk100m_reg
(E1)
uc_ioe2_dio485_o
Digital output
_clk100m_reg
signal (digital I/O
E2)
uc_ioe2_dio485_e
Digital I/O control
n_clk100m_reg
(E2)
uc_ioe0_andat_clk
D/A conversion
100m_reg
value (E0)
uc_ioe0_andat_en
D/A conversion
_clk100m_reg
value enable (E0)
uc_ioe0_ldac_clk1
LDAC output (E0)
00m_reg
uc_ioe1_andat_clk
D/A conversion
100m_reg
value (E1)
uc_ioe1_andat_en
D/A conversion
_clk100m_reg
value enable (E1)
uc_ioe1_ldac_clk1
LDAC output (E1)
00m_reg
uc_ioe2_andat_clk
D/A conversion
100m_reg
value (E2)
uc_ioe2_andat_en
D/A conversion
_clk100m_reg
value enable (E2)
uc_ioe2_ldac_clk1
LDAC output (E2)
00m_reg
uc_logdat_clk100
Logging data
m_reg
uc_logen_clk100m
Logging enable
_reg
uc_logend_clk100
Logging end trigger
m_reg
uc_loguserpulse_cl
User sampling
k100m_reg
pulse
uc_err_clk100m_re
User circuit: error
g
signal
cpu_intpl_out
General-purpose
output
uc_sampling_tmgp
User circuit: Data
ulse_clk100m_1sh
sampling pulse
ot_reg
uc_rs_usr_alrreg_
Always read
00_clk100m_reg
register 0
uc_rs_usr_alrreg_
Always read
01_clk100m_reg
register 1
uc_rs_usr_alrreg_
Always read
02_clk100m_reg
register 2
uc_rs_usr_alrreg_
Always read
03_clk100m_reg
register 3
uc_rs_usr_alrreg_
Always read
04_clk100m_reg
register 4
Bit
Input/
Polarity
Initial
width
output
value
1
Output
0H
1
Output
0H
1
Output
0H
1
Output
0H
1
Output
0H
1
Output
0H
32
Output
000000
00H
1
Output
H
0H
2
Output
0H
32
Output
000000
00H
1
Output
H
0H
2
Output
0H
32
Output
000000
00H
1
Output
H
0H
2
Output
0H
432
Output
ALL0H
1
Output
H
0H
1
Output
H
0H
1
Output
H
0H
1
Output
H
0H
3
Output
7H
6
Output
H
0H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
16
Output
0000H
Appendix 5 List of User Circuit Block Terminals
1shot
Sync clock
Feq
Clock
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
100MHz
clk100m
APPX
631
A
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Troubleshooting
