Z-80 Architecture - ZiLOG Z80 Handbook

CHAPTER 2
Z-80 Architecture
The architecture of the Z-80 is shown in Fig. 2-1. Thirteen CPU
and system control signals are sent to or generated in the instruction
decode and CPU control portion of the microprocessor. The data bus
is eight bits wide and is the path for all data transferred between
external memory and input/output devices and CPU registers. The
address bus is sixteen bits wide. Normally the address bus would
specify an external memory address of 0 to 65535 (0 to 64K - 1)
since the Z-80 has a full complement of input/output instructions
and no "memory-mapped" input/output would be required. (In
memory-mapped input/output, a portion of the memory addresses
must be dedicated to addresses of input/output devices).
The main path for data within the CPU is an internal data bus
which connects the CPU registers, arithmetic and logical unit, data
bus control, and instruction register. The arithmetic and logical unit
performs addition, subtraction, logical functions of ANDing, ORing,
and exclusive ORing, and shifting operations between two 8-bit
operands. In addition, binary-coded decimal (bcd) operations may
be performed under control of a Decimal Adjust Accumulator in-
struction.
GENERAL-PURPOSE REGISTERS
The Z-80 registers consist of fourteen general-purpose 8-bit regis-
ters designated A, B, C, D, E, H, and L and A', B', C', D', E', H',
and L'. Only one set of seven registers and the corresponding flag
register F or F' can be active at any given time. A special Z-80 in-
struction selects A and F or A' and F', while a second instruction
selects B, C, D, E, H, L, or B', C', D', E', H', or L'. The possible com-
15