Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 296

20.3 Registers and Register Details
20.3.1.2 16-bit free-run timer control status register
16-bit Timer Control Status Register
bit
Address: 00006E
H
Read/write
Initial value
[bit 7] Reserved bit
Always write '0' to this bit.
[bit 6] IVF
This bit is an interrupt request flag of the 16-bit free-run timer.
If the 16-bit free-run timer overflows, or if the counter is cleared by a match with compare register 0 in a
certain mode, '1' is written to this bit.
An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set.
This bit is cleared by writing '0.' Writing '1' has no effect.
'1' is always read by a read-modify-write instruction.
[bit 5] IVFE
IVFE is an interrupt enable bit of the 16-bit free-run timer. While '1' is written to this bit, an interrupt is
issued if '1' is written to the interrupt flag (bit 5: IVF).
[bit 4] STOP
The STOP bit is used to stop the 16-bit free-run timer.
Writing '1' to this bit stops the timer. Writing '0' starts the timer.
* The output compare operation stops when the 16-bit free-run timer stops.
276 Chapter 20: 16-Bit I/O Timer
7 6 5
Reserved IVF IVFE
R/W R/W R/W
0 0 0
0 No interrupt request (default)
1 Interrupt request
0 Interrupt disabled (default)
1 Interrupt enabled
0 Counting enabled (operation) (default)
1 Counting disabled (stop)
4 3 2
STOP MODE CLR
R/W R/W R/W
0 0 0
1 0
Bit Number
CLK1 CLK0 TCCS
R/W R/W
0 0
MB90580 Series