Figure 13.3C Registers Of Ie Bus (3/3) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Master address read register (MARH, MARL)
Address: 00007D
H
Read/write
Initial value
Address: 00007C
H
Read/write
Initial value
Multiaddress, control bit read register (DCRR)
Address: 00007F
H
Read/write
Initial value
Telegraph length read register (DERR)
Address: 00007E
H
Read/write
Initial value
Read data buffer (RDB)
Address: 000081
H
Read/write
Initial value
Write data buffer (WDB)
Address: 000080
H
Read/write
Initial value
MB90580 Series
15 14 13
Reserved Reserved Reserved
(R) (R)
(R)
(1) (1)
(1)
7 6
MA07 MA06 MA05
(R) (R)
(R)
(X) (X)
(X)
15 14
DO3 DO2 DO1
(R) (R) (R)
(0)
(0) (0)
7 6 5
DE7 DE6 DE5
(R) (R) (R)
(X) (X) (X)
15 14
RD7 RD6 RD5
(R) (R) (R)
(X) (X) (X)
7 6 5
WD7 WD6 WD5
(W) (W) (W)
(X) (X)

Figure 13.3c Registers of IE BUS (3/3)

12 11
MA11
Reserved
(R) (R)
(1) (X)
5 4 3
MA04 MA03
(R)
(R)
(X)
(X)
13 12 11
DO0 C3
(R)
(R)
(X)
(X)
4 3
DE4 DE3
(R)
(R)
(X)
(X)
13 12 11
RD4 RD3
(R)
(R)
(X)
(X)
4 3
WD4 WD3
(W) (W)
(X) (X) (X)
13.3 Registers and Register Details
10 9 8
MA10 MA09 MA08
(R)
(R) (R)
(X)
(X) (X)
2 1 0
MA02 MA01 MA00
(R)
(R) (R)
(X)
(X) (X)
10 9 8
C2 C1 C0
(R) (R) (R)
(X) (X) (X)
2 1 0
DE2 DE1 DE0
(R) (R) (R)
(X) (X) (X)
10 9 8
RD2 RD1 RD0
(R) (R) (R)
(X) (X) (X)
2 1 0
WD2 WD1 WD0
(W) (W) (W)
(X) (X) (X)
Chapter 13: IE Bus
Bit Number
MARH
Bit Number
MARL
Bit Number
DCRR
Bit Number
DERR
Bit Number
RDB
Bit Number
WDB
145