Regiaters And Register Details; Figure 18.3A Register Of Pulse Width Counter Timer - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

18.3 Regiaters and Register Details

PWC Control Status Register (Upper Byte)
Address : 000055
Read/write
Initial value
PWC Control Status Register (Lower Byte)
Address : 000054
Read/write
Initial value
PWC Data Buffer Register (Upper Byte)
Address : 000057
Read/write
Initial value
PWC Data Buffer Register (Lower Byte)
Address : 000056
Read/write
Initial value
Divide Ratio Control Register
Address : 000058
Read/write
Initial value
PWC Noise Cancelling register
Address : 000086
Read/write
Initial value
MB90580 Series
15 14 13
H STRT STOP EDIR
(R/W) (R/W) (R)
(0) (0) (0)
7 6 5
CSK1
CSK0 PIS1
H
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14 13
H
(R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
H
(R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
—
— —
H
(-) (-) (-)
(-) (-) (-)
7 6 5
—
— —
H
(-) (-) (-)
(-) (-) (-)

Figure 18.3a Register of Pulse Width Counter Timer

18.3 Regiaters and Register Details
12 11 10
EDIE OVIR OVIE
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
PIS0 S/C
MOD2
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
(R/W) (R/W) (R/W)
(X) (X) (X)
4 3 2
(R/W) (R/W) (R/W)
(X) (X) (X)
4 3 2
— —
—
(-) (-) (-)
(-) (-) (-)
4 3 2
— —
SW1
(-) (-) (R/W)
(-) (-) (0)
Chapter 18: Pulse Width Counter (PWC) Timer
Bit number
9 8
PWCSR
ERR POUT
(HIGH)
(R) (R/W)
(0) (0)
Bit number
1 0
PWCSR
MOD1 MOD0
(LOW)
(R/W) (R/W)
(0) (0)
Bit number
9 8
PWCR
(HIGH)
(R/W) (R/W)
(X) (X)
Bit number
1 0
PWCR
(LOW)
(R/W) (R/W)
(X) (X)
Bit number
1 0
DIV1 DIV0 DIVR
(R/W) (R/W)
(0) (0)
1 0
Bit number
RNCR
SW0 EN
(R/W) (R/W)
(0) (0)
243