Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 60

3.2 External Memory Access
3.2.2.3 Bus control signal selection register
Bus control signal selection register
Address: 0000A7
Read/write
Initial value
This register is used to set the bus control function in external bus mode.
This register cannot be accessed when the device is in single chip mode. In that case, all pins are used as
I/O ports regardless of the value of this register.
All bits of this register are write-only bits. '1' is always read from these bits.
[bit 15]: CKE
This bit controls the external clock (CLK) output as described below.
0
1
This bit is initialized to '0' upon a reset.
[bit 14]: RYE
This bit controls the external ready (RDY) input as described below.
0
1
This bit is initialized to '0' upon a reset.
[bit 13]: HDE
This bit specifies whether to enable I/O of hold-related pins. This bit controls the hold request input
(HRQ) and hold acknowledge output (HAKX) pins as described below.
0
1
This bit is initialized to '0' upon a reset.
[bit 12]: IOBS
This bit specifies the bus size when an area between 0000C0H and 0000FFH is externally accessed in
16-bit external data bus mode. The size is controlled as described below.
0
1
This bit is initialized to '0' upon a reset.
40 Chapter 3: Memory
15 14
CKE RYE
H
(W) (W)
(0) (0)
I/O port (P37) operation (clock output disabled)
Clock signal (CLK) output enabled
I/O port (P36) operation (external RDY input disabled) [default]
External ready (RDY) input enabled
I/O port (P35 and P34) operation (Hold function I/O disabled) [default]
Hold request (HRQ) input/hold acknowledge (HAKX) output enabled
16-bit bus size access [default]
8-bit bus size access
13 12 11
HDE IOBS HMBS
(W) (W)
(W)
(0)
(0)
(0)
10 9 8
—
WRE LMBS
(W) (W) (-)
(0) (0) (-)
MB90580 Series
Bit No.
ECSR