Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 22

1.1 Features
• Timers
18-bit Timebase counter/watchdog timer: 1 channel
Watch-dog timer : 1 channel
15-bit Watch timer : 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
16-bit re-load timer: 3 channels
16-bit PWC timer (with noise filter) : 1 channel
16-bit I/O timer (16-bit free-run timer): 1 channel
• Input capture (ICU) : 4 channels
Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge
input to the pin.
• Output compare (OCU) : 2 channels
Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit
free-run timer counter value and the compare setting value.
• UART : 5 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
• TP/external interrupt circuit : 8 channels
A module for starting extended intelligent I/O service (EI
by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• Clock monitor function
Output the clock to I/O port (Dividing the machine clock by 2 to 2
• ROM correction module
Replace the internal ROM code by small external circuit.
• ROM mirroring module
Used to increase the coding efficiency.
• 10-bit A/D converter : 8 channels
10-bit resolution can be selectively used.
Starting by an external trigger input.
• 8-bit D/A converter : 2 independent channels
8-bit resolution.
R-2R typet.
• Package
LQFP-100, QFP-100
• Process
CMOS technology
2 Chapter 1: Overview
2
OS) and generating an external interrupt triggered
8
.
MB90580 series