Output Compare Timing - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

20.5.2 Output compare timing

In output compare operation, a compare match signal is generated when the free-run timer value matches
the specified compare register value. The output value can be reversed and an interrupt can be issued.
The output reverse timing upon a compare match is synchronized with the counter count timing.
Compare operation upon update of compare register
When the compare register is updated, comparison with the counter value is not performed.
Counter value
Compare register 0
value
Compare register 0
write
Compare register 1
value
Compare register 1
write
Interrupt timing
Counter value
Compare register
value
Compare match
Interrupt
Output pin change timing
Counter value
Compare register
value
Compare match
signal
Pin output
MB90580 Series
N N+1
M
M
Compare 0 stop
N
N N+1
N+2
No match signal is generated.
N+1
N
N
N
Chapter 20: 16-Bit I/O Timer
20.5 Timing
N+3
N+3
Compare 1 stop
N+1
N+1
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