Appendix B Instructions; Addressing; Effective Address Field; Table B.1.1A Effective Address Field - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

APPENDIX B:
Instructions
B.1 Addressing
2
In the F MC-16LX, the address format is determined by either the instruction's effective address
specification, or by the instruction code itself (implied addressing).
B.1.1 Effective address field
The address formats specified in the effective address field are shown in Table B.1.1a.
Code
00 R0
01 R1
02 R2
03 R3
04 R4
05 R5
06 R6
07 R7
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

Table B.1.1a Effective Address Field

Notation
RW0 RL0
RW1 (RL0)
RW2 RL1
Register direct
RW3 (RL1)
Starting from the left, "ea" corresponds to the
RW4 RL2
byte, word and long-word types.
RW5 (RL2)
RW6 RL3
RW7 (RL3)
@RW0
@RW1
Register indirect
@RW2
@RW3
@RW0+
@RW1+
Register indirect with post-incrementing
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
Register indirect with 8-bit displacement
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
Register indirect with 8-bit displacement
@RW6+disp8
@RW7+disp8
@RW0+disp16
@RW1+disp16
Register indirect with 16-bit displacement
@RW2+disp16
@RW3+disp16
@RW0+RW7 Register indirect with index
@RW1+RW7 Register indirect with index
@PC+disp16 PC indirect with 16-bit displacement
addr16 Direct address
Address format Default bank
None
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
DTB
DTB
PCB
DTB