Registers And Register Details; Program Address Detect Register 0/1 (Padr0/Padr1); Figure 21.3A Registers Of Rom Correction Module - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

21.3 Registers and Register Details

21.3 Registers and Register Details
Program Address Detect Register 0/1
PADR0 1FF2H/1FF1H/1FF0H
PADR1 1FF5H/1FF4H/1FF3H
Program Address Detect Control Status Register
Address : 009E
Read/write
Initial value

21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1)

These registers hold the addresses for the comparison with program counter. If there is an agreement and
when the corresponding ADCSR interrupt enable bit is at ' 1', this module demands the CPU to execute
the INT9 instruction.
If the corresponding interrupt enalble bit is ' 0', nothing will occur even there is a match.
Program Address Detect Register 0/1
PADR0 1FF2H/1FF1H/1FF0H
PADR1 1FF5H/1FF4H/1FF3H
The correspondance to the PACSR will be as follows.
292 Chapter 21: ROM Correction Module
byte
7 6
— —
H
(–) (–)
(–) (–)

Figure 21.3a Registers of ROM Correction Module

byte
ROM correction register
PADR0
PADR1
byte
5 4 3
— — AD1E
(–) (–) (R/W)
(0) (0) (0)
byte
Compare enable bit
byte
access
initial value
undefined
R/W
undefined
R/W
2 1 0
— AD0E —
PACSR
(–) (R/W) (–)
(0) (0) (0)
byte
access initial value
R/W
R/W
AD0E
AD1E
MB90580 Series
Bit number
undefined
undefined