Operations; 16-Bit Free-Run Timer - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

20.4 Operations

20.4.1 16-bit free-run timer

The 16-bit free-run timer starts counting from counter value '0000' after the reset is released. The counter
value is used as the reference time for the 16-bit output compare and 16-bit input capture operations.
The counter value is cleared in the following conditions:
• When an overflow occurs.
• When a match with output compare register 0 occurs. (This depends on the mode.)
• When '1' is written to the CLR bit of the TCCS register during operation.
• When '0000' is written to the TCDC register during stop.
• Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared due to a match with
compare register 0. (Compare match interrupts can be used only in an appropriate mode.)
Clearing the counter by an overflow
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
Clearing the counter upon a match with output compare register 0
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare
register value
Interrupt
MB90580 Series
Overflow
Match
BFFF
H
20.4 Operations
Time
Match
Chapter 20: 16-Bit I/O Timer
Time
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