Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 325

Address
5A
H
Output Compare Register 0
5B
H
5C
H
Output Compare Register 1
5D
H
5E
Output Compare Control Status Register 0
H
5F
Output Compare Control Status Register 1
H
60
H
Input Capture Register 0
61
H
62
H
Input Capture Register 1
63
H
64
H
Input Capture Register 2
65
H
66
H
Input Capture Register 3
67
H
Input Capture Control Status Register
68
H
69
H
Input Capture Control Status Register
6A
H
6B
H
6C
16-bit Timer Data Register (Low)
H
6D
16-bit Timer Data Register (High)
H
6E
16-bit Timer Control Status Register
H
6F Rom Mirror Function Select Register
H
70 Unit Address Register (Low)
H
71 Unit Address Register (High)
H
72 Slave Address Register (Low)
H
Slave Address Register (High)
73
H
74 Telegraph Length Set Register
H
75 Multiaddress, Control Bit Set Register
H
76 Command Register (Low)
H
77 Command Register (High)
H
78 Status Register (Low)
H
79 Status Register (High)
H
7A Lock Read Register (Low)
H
7B Lock Read Register (High)
H
7C Master Address Read Register (Low)
H
7D Master Address Read Register (High)
H
7E Telegraph Length Read Register
H
7F Multiaddress, Control Bit Read Register
H
80
H
81
H
82 Serial mode register 3
H
83 Serial control register 3
H
Serial input register/serial output register 3
84
H
85 Serial status register 3
H
86
PWC Noise cancelling register
H
87 Clock division control register 3
H
MB90580 Series
Table A.1a I/O map (Continued)
Register
Ch0,1
Reserved area
Ch2,3
Write Data Buffer
Read Data Buffer
Abbreviation Access
OCCP0 R/W
OCCP1 R/W
OCS0 R/W
OCS1 R/W
R
IPCP0
R
R
IPCP1
R
R
IPCP2
R
R
IPCP3
R
ICS01 R/W
ICS23 R/W
Reserved area
TCDTL R/W
TCDTH R/W
TCCS R/W
ROMM W
MAWL R/W
MAWH R/W
SAWL R/W
SAWH R/W
DEWR R/W
DCWR R/W
CMRL R/W
CMRH R/W
STRL R
STRH R/W
LRRL R
LRRH R
MARL R
MARH R
DERR R
DCRR R
WDB R/W
RDB R
SMR3 R/W
SCR3 R/W
SIDR/
R/W
SODR3
SSR3 R/W
RNCR R/W
CDCR3 R/W
Resource
Output Compare
(Channel 0 To 1)
Input Capture (Channel 0
To 3)
Free Run Timer
ROM mirroring Module
IEBus Interface
UART3
PWC noise filter
Communication prescaler 3
Appendix A: I/O Map
A.1 I/O Map
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
0000--00
---00000
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
00000000
00000000
---- ---1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
XX00000
000000XX
0011XXXX
00000000
XXXXXXXX
XXX0XXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000XXXXX
XXXXXXXX
XXXXXXXX
00000000
00000100
XXXXXXXX
00001-00
---- -000
0---1111
305