Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 216

14.3 Registers and Register Details
This bit controls the PPG counter underflow as described below.
PUF0
0
1
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, '1' is written to this bit when an underflow
occurs as a result of the ch0 counter value becoming between 00H and FFH. In 16-bit PPG 1ch mode,
'1' is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming
between 0000H and FFFFH. To set this bit to '0,' write '0.' Writing '1' to this bit is invalid. Upon a read
operation during a read-modify-write instruction, '1' is read.
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 0] This is a reserved bit.
When setting PPGC0, always set this bit to 1.
196 Chapter 14: 8/16-Bit PPG
PPG counter underflow is not detected
PPG counter underflow is detected
Operation
[initial value]
MB90580 Series