Command Register Lower Byte (Cmrl); Table 13.3.2A Interval For The Occurrence Of Data Transmit Interrupt; Table 13.3.2B Interval For The Occurrence Of Data Transmit Interrupt; Table 13.3.2C Interval For The Occurrence Of Data Transmit Interrupt - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3 Registers and Register Details

13.3.2 Command register lower byte (CMRL)

Command register lower byte (CMRL)
Address: 000076
H
Read/write
Initial value
[bit 7] RXS
RX input pin polarity selected for external driver/receiver.

Table 13.3.2a Interval for the occurrence of data transmit interrupt

RXS
0
1
[bit 6] TXS
TX output pin polarity selected for external driver/receiver.

Table 13.3.2b Interval for the occurrence of data transmit interrupt

TXS
0 TX pin as postive logic output. Logic '1' is high level and Logic '0' is Low level.
1 TX pin as negative logic output. Logic '1' is low level and Logic '0' is high level.
Note1: For MB90580 series, during reset, TX pin will output 'L'. If the driver/receiver used is
in positive logic (Driver/receiver enable at 'L'), TX outputs 'L' from reset to bit setting
that will generate a communication error when there is a communication between
other communication units. When it happens, it needs a outside circuit to input 'H' to
the driver/receiver from reset to bit setting.
[bit 5, 4] TIT1, TIT0 (Data transmit interrupt control bits)
These bits control the time interval of the occurrence of interrupt for writing transmit data in write data
buffer (WDB).

Table 13.3.2c Interval for the occurrence of data transmit interrupt

TIT1
148 Chapter 13: IE Bus
7 6 5
RXS TXS TIT1
(R/W) (R/W) (R/W)
(1) (1) (0)
RX pin as postive logic input. Logic '1' is high level and Logic '0' is Low level.
RX pin as negative logic input. Logic '1' is low level and Logic '0' is high level.
TIT0
0 0 More than one byte data can be written in WDB
0 1 More than two byte data can be written in WDB
1 0 More than four byte data can be written in WDB
1 1 Eight byte data can be written in WDB
4 3 2
TIT0 CS1 CS0
(R/W) (R/W) (R/W)
(0) (0)
(0)
RX input status
TX output
Timing for interrupt occurs
1 0 Bit Number.
RDBC WDBC CMRL
(R/W) (R/W)
(0) (0)
MB90580 Series