Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 335

B.2 Instruction Set
• Number of execution cycles
The number of cycles required for the execution of an instruction is obtained by summing the value
shown in the table for the "number of cycles" for the instruction in question, the compensation value
(which depends on certain conditions), and the "number of cycles" needed for the program fetch.
When fetching a program in memory connected to the 16-bit bus, such as on-chip ROM, a program
fetch is performed for each two-byte (word) boundary crossed by the instruction being executed;
therefore, if there is any interference with data access, etc., the number of execution cycles increases.
When fetching a program in memory connected to the 8-bit external data bus, a program fetch is
performed for each byte of the instruction being executed; therefore, if there is any interference with
data access, etc., the number of execution cycles increases.
In CPU intermittent operation, each access to general-purpose registers, internal ROM, internal RAM,
internal I/O functions or external bus causes the CPU clock to pause for a fixed number of cycles
determined by the CG1/CG0 bits in the low power consumption mode control register. For this reason,
the number of machine clock cycles required to execute an instruction under CPU intermittent opera-
tion is the normal number of cycles plus an offset number of cycles that is derived by multiplying the
number of access operations by the length (in cycles) of the fixed pause.
MB90580 Series APPENDIX B: Instructions 315