Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 151

[bit 13] FRE (Framing error)
This interrupt request flag is set when a framing error occurs during reception.
To clear a set flag, write '0' to the REC bit (bit 10) of the SCR register.
When this bit is set, the data in SIDR is invalid.
No framing error has occurred.
0
A framing error has occurred.
1
[bit 12] RDRF (Receiver data register full):
This interrupt request flag indicates that the SIDR register contains received data.
This flag is set when received data is loaded into the SIDR register. This flag is automatically cleared
when the SIDR register is read.
No received data exists.
0
Received data exists.
1
[bit 11] TDRE (Transmitter data register empty):
This interrupt request flag indicates that transmission data can be written into the SODR register.
This flag is cleared when transmission data is written into the SODR register. Then, when the written
data is loaded into the transmission shifter and transfer starts, this flag is set again, indicating the next
transmission data item can be written.
Writing transmission data is disabled.
0
Writing transmission data is enabled.
1
0: Writing transmission data is disabled.
1: Writing transmission data is enabled.
[bit 9] RIE (Receiver interrupt enable):
This bit is used to control reception interrupts.
Interrupts are disabled
0
Interrupts are enabled.
1
Note: Reception interrupt causes include normal reception by RDRF in addition to errors
due to PE, ORE, and FRE.
[bit 8] TIE (Transmitter interrupt enable):
This bit is used to control transmission interrupts.
Interrupts are disabled
0
Interrupts are enabled.
1
Note: Transmission interrupt causes include transmission requests by TDRE.
MB90580 Series
12.3 Register and Register Details
[initial value]
[initial value]
[initial value]
[initial value]
[initial value]
Chapter 12: UART 131