Figure 14.4B 8+8 Ppg Output Operation Waveform - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

(4) Count clock selection
The count clock used for the operation of this block is supplied from a peripheral clock or time base
counter. The count clock can be selected from six types.
Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPGOE register, and ch1 clock at bit 7 to S (PCS2 to 0) of
the PPGOE register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock
from a time base counter.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the value in bit 14 (PCS1) of the
PPGC1 register is invalid. The register is invalid because ch1 PPG receives a count clock from ch0.
When the time base counter input is used, the first count cycle after a trigger or a stop may be shifted. The
cycle may also be shifted if the time base counter is cleared during operation of this module.
In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first
count cycle may be shifted.
(5) Pulse pin output control
The pulses generated by this module can be output from external pins PPG0 and PPG1.
To output the pulses from an external pin, write '1' to the bit corresponding to each pin. Use bit 5 (PE0) of
the PPGC0 register for the PPG0 pin, bit 13 (PE1) of the PPGC1 register for the PPG1 pin. When '0' is
written to these bits (default), the pulses are not output from the corresponding external pins; the pins work
as general-purpose ports.
In 16-bit PPG mode, the same waveform is output from PPG0 and PPG1. Thus, the same output can be
obtained by enabling any external pin.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG0, while
the 8-bit PPG waveform is output from PPG1. The figure below is a diagram of output waveforms in this
mode.
Ph0
PPG0
1
PPG
Pl0 = T x (L0+1)
Ph0 = T x (L0+1)
Pl1 = T x (L0+1) x (Ll+1)
Ph1 = T x (L0+1) x (Hl+1)
Note : Set the same value in ch0 PRLL and ch0 PRLH.
MB90580 Series
Pl0
Ph1 Pl1

Figure 14.4b 8+8 PPG output operation waveform

L0 : ch0 PRLL value and ch0 PRLH value
L1 : ch1 PRLL value
H1 : ch1 PRLH value
T : Input clock cycle
Ph0 : PPG0 high pulse width
Pl0 : PPG0 low pulse width
Ph1 : PPG1 high pulse width
Pl1 : PPG1 low pulse width
Chapter 14: 8/16-Bit PPG
14.4 Operations
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