18.2 Block Diagram
18.2 Block Diagram
PWCR read
16
16
Count start edge
Count end edge
Count end
interrupt request
Overflow interrupt
request
15
242
Chapter 18: Pulse Width Counter (PWC) Timer
Error detection
PWCR
16
Reload
Data transfer
Overflow
16-bit up-count timer
Control circuit
Start edge
End edge
selection
selection
Edge detect
PIS1
ERR
PIS0
PWCSR
Figure 18.2a lock Diagram of Pulse Width Counter Timer
ERR
16
Clock
Timer clear
Count enable
Divider
ON/OFF
CKS1
CKS0
Divide ratio
selection
2
DIVR
Internal clock
(machine clock/4)
2
2
Clock divider
3
2
CKS1
Divider clear
CKS0
8-bit
divider
Overflow
F.F
MB90580 Series
PWC
POT