Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 6

6.4.3 Watch mode ........................................................................................................................69
6.4.4 Stop mode ...........................................................................................................................69
6.4.5 Hardware standby mode .....................................................................................................70
6.4.6 CPU intermittent operation function .....................................................................................70
6.4.7 Setting the main clock oscillation stabilization waiting period ..............................................71
6.4.8 Switching the machine clock ...............................................................................................71
6.4.9 State transition .....................................................................................................................73
Chapter 7 Interrupt ...........................................................................................................................................81
7.1 Outline ...........................................................................................................................................81
7.2 Causes of Interrupt ........................................................................................................................82
7.3 Interrupt Vector .............................................................................................................................83
7.4 Hardware Interrupt ........................................................................................................................84
7.4.1 Overview ..............................................................................................................................84
7.4.2 Structure ..............................................................................................................................84
7.4.3 Operation .............................................................................................................................84
7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed ......................87
7.4.5 Interrupt Inhibit Instruction ...................................................................................................87
7.4.6 Multiple Interrupts ................................................................................................................87
7.4.7 Register Saving In Stack Upon Interrupt .............................................................................87
7.4.8 Precaution in Using Hardware Interrupt ..............................................................................87
7.5 Software Interrupt ..........................................................................................................................88
7.5.1 Overview ..............................................................................................................................88
7.5.2 Structure ..............................................................................................................................88
7.5.3 Operation .............................................................................................................................89
7.5.4 Others ..................................................................................................................................89
7.6 Extended intelligent I/O service (EI2OS) .......................................................................................90
7.6.1 Overview ..............................................................................................................................90
7.6.2 Structure ..............................................................................................................................91
7.6.3 Operation .............................................................................................................................97
7.6.4 EI2OS Execution Time ........................................................................................................99
7.7 Exceptions ...................................................................................................................................100
7.7.1 Exception due to execution of an undefined instruction ....................................................100
Chapter 8 Parallel Ports .................................................................................................................................101
8.1 Outline .........................................................................................................................................101
8.2 Block Diagram .............................................................................................................................102
8.3 Registers and register details ......................................................................................................103
8.3.1 Port data register ...............................................................................................................104
8.3.2 Port direction registers .......................................................................................................105
8.3.3 Output pin register .............................................................................................................106
8.3.4 Input resistor register .........................................................................................................106
8.3.5 Analogue Input Enable Register ........................................................................................107
8.3.6 Low Noise Output Select Register .....................................................................................107
Chapter 9 DTP/External Interrupt ..................................................................................................................109
9.1 Outline .........................................................................................................................................109
9.2 Block Diagram .............................................................................................................................109
9.3 Registers and Register Details ....................................................................................................110
9.3.1 Interrupt/DTP enable register (ENIR: Enable interrupt request register) ...........................110
9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) ..........................111
9.3.3 Request level setting register (ELVR: External level register) ...........................................111
vi MB90580 Series