Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 218

14.3 Registers and Register Details
[bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit
This bit controls the PPG counter underflow as described below.
PUF1
0
1
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, '1' is written to this bit when an underflow
occurs as a result of the ch1 counter value becoming between 00H and FFH. In 16-bit PPG 1ch mode,
'1' is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming
between 0000H and FFFFH. To set '0' in this bit, write '0.' Writing '1' to this bit is invalid. Upon a read
operation during a read-modify-write instruction, '1' is read.
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 10, 9] MD2, 1 (PPG count mode): Operation mode selection bit
This bit selects the PPG timer operation mode as described below.
MD1 MD0
0
0
1
1
This bit is initialized to '00' upon a reset. This bit is readable and writable.
Note: Do not set '10' in this bit.
Note: To write '01' to this bit, ensure that '01' is not written to the PEN0 bit of PPGC0 or
PEN1 bit of PPGC1.
Write '11' or '00' in both the PEN0 and PEN1 bits simultaneously.
Note: To write '11' to this bit, update PPGC0 and PPGC1 by word transfer and write '11'
or '00' to both the PEN0 and PEN1 bits simultaneously.
[bit 8] This is a reserved bit.
When setting PPGC0, always write 1 to this bit.
198 Chapter 14: 8/16-Bit PPG
PPG counter underflow is not detected
PPG counter underflow is detected
Operation mode
0 8-bit PPG 2ch independent mode
1 8-bit prescaler + 8-bit PPG 1ch mode
0 Reserved (setting inhibited)
1 16-bit PPG 1ch mode
Operation
[initial value]
MB90580 Series