Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 11

FIGURES
Chapter 1 Overview ............................................................................................................................................1
Figure 1.3a Block Diagram of MB90580 Series .................................................................................... 4
Figure 1.4a Pin Assignment of MB90580 (LQFP-100).......................................................................... 5
Figure 1.4b Pin Assignment of MB90580 (QFP-100)............................................................................ 6
Figure 1.6a Using external clock ......................................................................................................... 14
Figure 1.6b Connection of Power pins ................................................................................................ 14
Chapter 2 CPU ..................................................................................................................................................15
Figure 2.1.1a Sample relationship between F2MC-16LX system and memory map .......................... 16
Figure 2.1.1b Sample linear addressing.............................................................................................. 17
Figure 2.1.1c Physical addresses of each space ................................................................................ 18
Figure 2.1.1d Sample allocation of multi-byte data in memory ........................................................... 19
Figure 2.1.1e Execution of MOVW A, 080FFFFH ............................................................................... 19
Figure 2.1.2a Special registers............................................................................................................ 20
Figure 2.1.2b General-purpose registers ............................................................................................ 21
Figure 2.1.2c Program counter............................................................................................................ 21
Figure 2.1.2d 32-bit data transfer ........................................................................................................ 22
Figure 2.1.2e AL-AH transfer .............................................................................................................. 22
Figure 2.1.2f Stack manipulation instruction and stack pointer ........................................................... 23
Figure 2.1.2g PS structure .................................................................................................................. 24
Figure 2.1.2h Condition code register configuration............................................................................ 24
Figure 2.1.2i Register bank pointer ..................................................................................................... 25
Figure 2.1.2j Interrupt level register..................................................................................................... 25
Figure 2.1.2k Generating a physical address in direct addressing mode............................................ 27
Figure 2.1.3a Interrupt disable instruction ........................................................................................... 29
Figure 2.1.3b Interrupt disable instructions and prefix codes.............................................................. 30
Figure 2.1.3c Consecutive prefix codes .............................................................................................. 30
Chapter 3 Memory ............................................................................................................................................31
Figure 3.1.3a Access areas and physical addresses in each bus mode............................................. 34
Figure 3.2.1a External bus pin control circuit ...................................................................................... 36
Figure 3.2.1a External memory access timing chart ........................................................................... 42
Figure 3.2.1b External memory access timing chart ........................................................................... 43
Figure 3.2.1c Ready timing chart ........................................................................................................ 44
Figure 3.2.1d Hold timing .................................................................................................................... 45
Chapter 4 Clock and Reset ..............................................................................................................................47
Figure 4.1a Clock generator circuit block diagram .............................................................................. 47
Figure 4.2a Reset cause bit block diagram ......................................................................................... 49
Figure 4.2b WDTC (watch-dog timer control register)......................................................................... 49
Figure 4.3a Source and destination of reset vector and mode data.................................................... 50
MB90580 Series xi