Fig. B.1.2A Register List Configuration - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

B.1 Addressing
(10) Accumulator indirect (@A)
This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and DTB
indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the address.
(11) I/O direct (io)
In this format, the memory address of the operand is specified directly by the 8-bit displacement value.
Regardless of the value of DTB and DPR, the I/O space from 000000
access space specification prefix has no effect on this addressing format.
(12) Long register indirect with displacement (@RLi + disp8
This format accesses the memory address indicated by the low-order 24 bits of the sum of the contents
of the general-purpose register RLi plus the displacement value. The displacement value is 8 bits, and
is added as a signed numeral.
(13) Compressed direct bit address (dir:bp)
This format specifies the low-order 8 bits of the memory address with the operand. In addition, bits 8 to
15 of the address are indicated by DPR. Finally, bits 16 to 23 of the address are indicated by DTB. The
bit position is indicated by ":bp", with larger numbers being closer to the MSB and smaller numbers
being closer to the LSB.
(14) I/O direct bit address (io:bp)
This format directly specifies a bit within a physical address from 000000
is indicated by ":bp", with larger numbers being closer to the MSB and smaller numbers being closer to
the LSB.
(15) Direct bit address (addr16:bp)
This format directly specifies any bit within a 64-kilobyte region. Bits 16 to 23 of the address are
indicated by DTB. The bit position is indicated by ":bp", with larger numbers being closer to the MSB
and smaller numbers being closer to the LSB.
(16) Register list (rlst)
This format specifies the register that is the target of a stack push/pop instruction.
312 APPENDIX B: Instructions
MSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is "1",
and is not selected when the corresponding bit is "0".

Fig. B.1.2a Register List Configuration

to 0000FF is accessed. The
H H
i = 0 to 3)
to 0000FF . The bit position
H H
LSB
MB90580 Series