Table 13.5.1A Time Required To Write Transmit Data To Wdb After Transmit Interrupt Has Occurred - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5. If error occurs during transmission or in multi-frame communication the number of data byte specified
in DEWR cannot be transmitted completely, the state code (3H) indicating transmission terminated
without all data transmitted is set in STRL:ST3-0. Transmit interrupt will occur. At this time, the content
of communication error can be known by checking the status of TSL, PEF, TE in status register
(STRH).
The interval between setting ST3-0 and the first data is transmitted out from WDB is shown below:

Table 13.5.1a Time required to write transmit data to WDB after transmit interrupt has occurred

Mode
Note :
1. Number of transmit bytes and transmit data can be set during the interrupt generated after the receiving
of control bits.
2. As the time between the WDB empty interrupt and the next telegraph bit transmit interrupt is very short,
thus it is recommended to take the following precautions when the first transmit data is required to write
into WDB.
• Only write data to WDB after the WDB empty confirmation.
• In case of setting the transmit data byte count, it is required to set the value within the time listed in
Table 13.5.1a. The default value of the transmit data byte count will transmit 256bytes.
• If at least 1 byte of data is not set within the time listed in below after the transmit interrupt, WDB will
be detected as empty. Error will be occurred after the transmission of telegraph field and the
communication will be terminated.
Slave status, lock address transmit
When the control bits 0H, 4H, 5H, 6H has been received from the master, the slave status, lock address
are automatically transmitted to the master. In this way, there is no need to write data into WDB, but it is
required to set 1H to the telegraph bit setting register.
(3) Master receive
The unit is set as master receive for getting data, slave status and lock address from the slave by first
sending control bits 0H, 3H, 4H, 5H, 6H or 7H. The sequences for operating as master receive are
described as below:
1. When the slave receives the control bits, it transmits the telegraph length bit. Then after the master
receives these telegraph length bits and returns the acknowledge bit, the number of received data byte
is written into the telegraph length read register (DERR). At this moment, no interrupt occurs.
2. After the acknowledge bit in telegraph length field is sent by the master, data reception will be started.
And for each received data byte, the master stores it in the read data buffer (RDB).
3. After eight bytes of data are received, the state code (5H) is set in ST3-0 of status register (STRL),
receive interrupt occurs.
4. When the last byte of data is received and stored in RDB within one communication frame, the state
code (5H) is set in ST3-0 and receive interrupt occurs. This interrupt will be generated even thought
RDB is not full.
5. If error is occurred during reception, or the maximium number of data byte has been received in one
communication frame, the master cannot received the number of data byte specified in telegraph field
and communication is terminated. The state code (7H) indicating master receive ends without all data
are received is set in ST3-0, and receive interrupt occurs.
MB90580 Series
Time (µS)
0 approx. 158
1 approx. 40
2 approx. 29
Number of cycles
approx. 1900
approx. 480
approx. 350
Chapter 13: IE Bus
13.5 Operation
175