Figure 12.4.5C Timing To Set Ore And Rdrf (Mode 2); Figure 12.4.5D Timing To Set Tdre (Modes 0 And 1); Figure 12.4.5E Timing To Set Tdre (Mode 2) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

12.4 Operations
Then, an interrupt request is issued to the CPU. If the ORE flag is active, the data in SIDR is invalid.
Reception interrupt
(4) Transmission in modes 0, 1, and 2
TDRE is cleared when a data item is written into the SODR register. When the data item is transferred
to the internal shift register and the next data item can be written, TDRE is set and an interrupt request
is issued to the CPU. If '0' is set in TXE (or additionally RXE in mode 2) of the SCR register during
transmission, '1' is set in TDRE of the SSR register. Then, the transmission shifter stops and the
transmission by UART is disabled. If '0' is set in TXE (or additionally RXE in mode 2) of the SCR reg-
ister during transmission, the data set in the SODR register is transmitted before transmission stops.
SODR write
TDRE
SOT0 interrupt
SOT0 output
SODR write
TDRE
SOT0 interrupt
SOT0 output
138 Chapter 12: UART
Data
ORE
RDRF

Figure 12.4.5c Timing to set ORE and RDRF (mode 2)

An interrupt request is issued to the CPU.
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
ST: Startbit D0 to D7: Databits

Figure 12.4.5d Timing to set TDRE (modes 0 and 1)

An interrupt request is issued to the CPU.
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

Figure 12.4.5e Timing to set TDRE (mode 2)

D7
D5 D6
SP: Stopbit
D0 to D7: Data bits
SP ST D0 D1 D2 D3
A/D
A/D: Address/data multiplexer
D4 D5 D6 D7
MB90580 Series