Status Register Upper Byte (Strh) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3.7 Status register upper byte (STRH)

Status register upper byte (STRH)
Address: 000079
H
Read/write
Initial value
[bit 15] COM (Communication status):
This bit indicates the communication status as described below.
0
1
When this bit is '0' and the PCOM bit in command register (CMRH) is written '1', this bit is set.
When communication ends, this bit will be cleared.
.
[bit 14] TE (Timing error):
This bit is set when timing error has occurred during communication. Writing '0' will clear this bit.
This bit is written '0' only, there is no meaning for writing '1'.
[bit 13] PEF (Parity error):
This bit is set when parity error has been detected.
0
1
In receive side, if this bit is set, the acknowledge bit will not be returned. This bit will be cleared after the
communication inhibit state is released.
[bit 12] ACK (Acknowledge bit):
This bit indicates
0 The acknowledge bit is '0'
1 The acknowledge bit is '1'
During normal communication, acknowlege bit will be returned after each data received correctly. This
bit will be cleared after communication inhibit state is released.
This bit has no meaning in multiaddress communication and the read value is indefined.
MB90580 Series
15 14 13
COM TE PEF
(R) (R/W) (R)
(0) (0) (X)
Communication is prohibited
Communication is enabled
No parity error
Parity error
13.3 Registers and Register Details
12 11 10
ACK RIF TIF
(R) (R/W) (R/W)
(X) (0)
(0)
9 8 Bit Number
TSL EOD STRH
(R) (R)
(0) (0)
Chapter 13: IE Bus 153