Instantiating The Reset Release Ip In Your Design; Gating The Pll Reset Signal - Intel Agilex Series Configuration User Manual

4. Including the Reset Release Intel FPGA IP in Your Design
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4.2. Instantiating the Reset Release IP In Your Design

The Reset Release IP is available in the IP Catalog in the Basic Functions
This IP has no parameters.
Complete the following steps to instantiate the Reset Release IP in your design.
1. In the IP Catalog, type
Figure 55. Locate Reset ReleaseIntel FPGA IP in IP Catalog
2. Double click the Reset Release Intel FPGA IP to add the Reset Release IP to your design.
3. In the New IP Variant dialog box, browse to your IP directory and specify a file name for the Reset Release IP. Then
click Create. The Reset Release IP is now included in your project.

4.3. Gating the PLL Reset Signal

In older FPGA device families, designs frequently used the PLL lock signal to hold the custom FPGA logic in reset until the PLL
locked. In newer Intel device families the lock time of PLLs can be less than the initialization time. In some cases the PLL may
lock before the device completes initialization. Consequently, if you use the locked output of the PLL to control resets in the
Intel Agilex device, you should gate the PLL reset input with
Send Feedback
in the search window to find the Reset Release Intel FPGA IP.
reset release
Configuration and Programming category.
as shown the figure.
nINIT_DONE
Intel ® Agilex ™ Configuration User Guide
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