Tck Termination, Dp System; Prdyx# Signal Termination; Execution Signals Routing Guidelines - Intel Pentium III Processor 512K Design Manual

Figure 7. TCK Termination, DP System
Execution Signal Layout Guidelines
Table 12. Execution Signals Routing Guidelines
Signal
PREQx#
PRDYx#
RESET#
Figure 8. PRDYx# Signal Termination
Design Guide
®
LV Intel Pentium
Figure 3. TCK Termination, DP System
Routing Notes
AGTL signal routing guidelines apply
The flight time of the RESET# signal from the closest processor
must be added to the arrival time of BCLK at the Debug Port.
Termination Voltage
Processor n
®
III Processor 512K Dual Processor Platform
Rt
Rs
Sample Layout
Figure 6 (a)
Figure 8
Figure 9
Debug Port
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